IS61DDB42M18A Description
1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid window. mon I/O read and write ports.
IS61DDB42M18A Key Features
- 1Mx36 and 2Mx18 configuration available
- On-chip delay-locked loop (DLL) for wide data valid
- mon I/O read and write ports
- Synchronous pipeline read with late write operation
- Double Data Rate (DDR) interface for read and
- Fixed 4-bit burst for read and write operations
- Clock stop support
- Two input clocks (K and K#) for address and control
- Two input clocks (C and C#) for data output control
- Two echo clocks (CQ and CQ#) that are delivered